Silicon Labs /EFR32MG24A610F1536IM40 /IADC0_S /SCANFIFOCFG

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Interpret as SCANFIFOCFG

31282724232019161512118743000000000000000000000000000000000000000000 (RIGHT12)ALIGNMENT0 (SHOWID)SHOWID0 (VALID1)DVL0 (DISABLED)DMAWUFIFOSCAN

DVL=VALID1, DMAWUFIFOSCAN=DISABLED, ALIGNMENT=RIGHT12

Description

SCAN FIFO configuration

Fields

ALIGNMENT

Alignment

0 (RIGHT12): ID[7:0], SIGN_EXT, DATA[11:0]

1 (RIGHT16): ID[7:0], SIGN_EXT, DATA[15:0]

2 (RIGHT20): ID[7:0], SIGN_EXT, DATA[19:0]

3 (LEFT12): DATA[11:0], 000000000000, ID[7:0]

4 (LEFT16): DATA[15:0], 00000000, ID[7:0]

5 (LEFT20): DATA[19:0], 0000, ID[7:0]

SHOWID

Show ID

DVL

Data Valid Level

0 (VALID1): When 1 entry in the scan FIFO is valid, set the SCANFIFODVL interrupt and request DMA.

1 (VALID2): When 2 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

2 (VALID3): When 3 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

3 (VALID4): When 4 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

4 (VALID5): When 5 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

5 (VALID6): When 6 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

6 (VALID7): When 7 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

7 (VALID8): When 8 entries in the scan FIFO are valid, set the SCANFIFODVL interrupt and request DMA.

DMAWUFIFOSCAN

Scan FIFO DMA Wakeup

0 (DISABLED): While in EM2 or EM3, the DMA controller will not be requested.

1 (ENABLED): While in EM2 or EM3, the DMA controller will be requested when the scan FIFO reaches its Data Valid Level. [DVL must be set to 0 (VALID1).]

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